1. Technical Field
This invention generally relates to the field of reliability testing of integrated circuits. More specifically, the invention relates to a methodology to establish a correlation between gate dielectric test site reliability and product gate reliability.
2. Related Art
In the reliability engineering of integrated circuits, it is necessary to predict product lifetimes and to calculate defect densities. To accomplish this in a short time, product samples may be subjected to environmental conditions that accelerate the failure modes that cause wearout. Typical methods for creating these stress conditions include the use of temperatures and voltages that exceed the operating temperatures and voltages when the circuit is in actual use.
As semiconductor dimensions continue to shrink, the gate dielectric thickness continues to decrease and the voltage is scaled down. The voltage scaling is at a lower rate than is the gate thickness decrease so that the field across the gate is increasing (V/tox). As the oxides continue to decrease, accurate prediction of the oxide reliability becomes more critical. However, also as the oxide continues to decrease, the correlation to the produce reliability seems to become more elusive.